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News 10 years Ago
 
Published by packi on

As mentioned earlier, my VHDL design didn’t fit the CPLD I’ve chosen to be used (namely the one I’ve got for free). This CPLD has 160 logic-cells while my design used 234 with not even all features implemented.
Reducing the RAM dataline-count from 24 to 16, using only two SRAMs instead of three, reduced the usage to 185 which, apparently, is still too much.

Using the chip usage analyzer I’ve seen that my communication logic used up 112 logic-cells.
I need to communicate to the PIC (micro-controller) to configure the trigger, arm the device, read back values, etc.
Since I’ve got eight lines to do so my initial idea was to send a command byte first, then multiple data bytes (clocked). This has inferred a gigantic state machine with only one transition from one to the other state.
Rewriting this piece of code to expect a command byte and a command word in the next clock-phase reduced the usage of logic-cells to a third.

Yeeehaw!

 
News 11 years Ago
 
Published by packi on

Back in August, during the spring break I’ve fooled around with KiCAD to create the schematics for the logic analyzer.


Since then I’ve finished the VHDL code, only to find out my CPLD has not enough macrocells to implement the design *ahrg*.

 
News 12 years Ago
 
Published by packi on

I’ve got the FPGAs on friday, but had no PLCC sockets to test them out. So I had to wait until the weekend passed by and the package from my local electronics (why do I feel the urge to write drugs, the parts are nearly that expensive) supplier arrived. The FPGAs I’ve received from a customer of ours are Atmel EMP7160S, getting programmed by a JTAG interface and the software from Atmel (Quartus II).

After everything was soldered in place and powered on my powersupply showed a current draw of 0.1 Amps so the circuit seemed to be consuming electrons. That was at 01:30 am.

The next day the FPGAs got programmed but since I had no spare oscillators I had to fetch some (you can place an order by phone or over the internet and collect them after two hours at the electronics suppliers place). After soldering the oscilator wrong twice (notice: the pins on the backside of a part appear to be mirrored ;-) and a coding simple frequency divider in VHDL I called it a day.

Fresh out of the HD an overview of the la:

32 Probes connected to four quad-input latches provide the input. The FPGA decides wheter or not to begin sampling.
If a trigger occurs the FPGA counts the addresses up on the A-Bus and drives the RAM to collect the data.
A PIC is used to communicate with the PC, setting trigger-masks and transfering the data measured.

Since the FPGA is a 84-pin PLCC-package I have about 60 input pins:
- 32 for the D-Bus
- 14 for the A-Bus
- ~9 for communicating
- 1 oscillator (GCLK1)
- 1 variable clock (freq-divider inside the FPGA)

This leaves me with 8 spare pins. Lets me think that I should really get me some thin wirewrap wires, the 0.22 mm^2 wire is just not suited to solder a piece with 84 pins ;-)

More to come…

 
Published by packi on

After hours of debugging communications between two PICs running at two different clockrates (well debugging is exaggerated it was more like looking at my no-memory oscope), I’ve decided to build myself a logic analyzer.

It should be capable to record 32k of Data at a sampling rate of ~10 Mhz (I won’t be using anything faster than that *fingers crossed*).. The samlping will be done by discrete logic doing the sampling and triggering. The serial interface will be handled by a PIC.

The basic design is already done and I’m in the process of simulation the logic-part of the circuit in VHDL (using the free version of Simili.